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A major advance in high-performance computing

​CEA-Leti, a CEA Tech institute, unveiled a state-of-the-art demonstrator chip for high-performance computing applications at ISSCC 2020. The low-cost, energy-efficient processor is built on an innovative multi-core system that is both modular and expandable.

Published on 7 May 2020

​High-performance computing (HPC) brings the combined power of several thousand processors to complex calculations and massively-parallel data processing. It is used in many industries for things like simulation. Leti augmented the capacity of its multi-core design by assembling the chiplets in a modular fashion using a concept called 3D integration. And the advantages are many: Not only does 3D integration reduce fabrication costs, it also allows heterogeneous functions like processing, memory, interfaces, and power management to be integrated onto a single chip.

Until recently, chiplets were assembled on a passive silicon interposer and connected to each other with simple metal strips, limiting the exchanges between cores. Leti developed a very innovative active interposer with a complete smart communication structure. The advance came as a result of research conducted under IRT Nanoelec. The chiplets can communicate with each other directly and without restrictions, regardless of their relative positions on the chip. This novel architecture boosts performance by facilitating communication and by making it possible to fit a much larger number of chiplets into a given system. It also allows additional functions to be tightly integrated with the processor cores so that the system can adapt to demand.

The 96-core demonstrator presented in February 2020 at ISSCC in San Francisco is arranged into six FDSOI chiplets 3D integrated onto the active 65 nm silicon interposer. There are many potential uses for the processor, one of which is integrating embedded artificial intelligence into autonomous vehicles.

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